Traditional complex processing systems are typically implemented using software running on a microprocessor in conjunction with multiple dedicated hardware blocks. Examples of processing systems employing mixed hardware/software descriptions include various MPEG (moving picture experts group) systems for processing multimedia content, such as MPEG-4 systems. In MPEG-4, standardization efforts have resulted in a software description of the compression algorithm from which mixed hardware/software implementations can be derived. In such systems, the hardware blocks are capable of performing complex functions more efficiently than such functions could be performed using pure software.
Supporting mixed hardware/software designs of a processing system with appropriate test and emulation platforms is critical to their deployment and acceptance in the industry. The conventional approach for testing and verifying such a design involves the application of a large number of test vectors to a software simulation of the design. As design complexity increases, however, simulation times are becoming prohibitively long on current desktop computers.
Another approach for testing and verifying designs involves the use of a test engine running on a standard computation device (e.g., a computer) in communication with hardware emulators. The hardware emulators allow for more accurate and efficient simulation of the hardware portion of the design. The hardware emulators may be implemented using hardware blocks in a programmable logic device (PLD), such as a field programmable gate array (FPGA). PLDs exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions.
The interface between the standard computation device and the hardware emulators is becoming increasingly important as processing system designs become more complex. For video and multimedia designs that involve an enormous amount of data to be processed, communication between a test engine running on a standard computation device and hardware emulators configured in a PLD is one of the primary bottlenecks that affect the test/verification process.
Accordingly, there exists a need in the art for an improved method and apparatus for communication between a processor and hardware blocks configured in a programmable logic device.